Last week a "bigpao007" user posted several slides in Chiphell forum, detailing features of upcoming Haswell-EP and Haswell-EN server microprocessors. As can be guessed from the name, new chips will be built on Haswell microarchitecture, and accommodate a number of technologies, specific to server market. According to the slides, future 22nm Xeons will integrate 10 or more CPU cores, and 2.5 MB of last level cache per each core. The slides state that the maximum size of the last level cache for the package is 35 MB, which means that the CPU may have up to 14 cores.
